1. Field of the Invention
The present invention is related to logical checking circuits for continuously monitoring the flow of data being transmitted from cards (boards or elements) of a main storage unit (MSU) or central processing unit (CPU). More particularly, the present invention is related to circuits for checking whether bus interface logic circuits on a card are properly transmitting or NOT transmitting data to a bus at the time designated by the central pipeline controller for transmitting data.
2. Description of the Prior Art
Computers and main storage units which employ bus architecture have a plurality of cards connected between the read bus and the write bus. Information originating at one card must be placed on a read or write bus before being available as input data to another card or an outside peripheral equipment. For example, data originating at a memory card is READ onto a read bus and routed to any of the other cards including a Port card which connects to other parts of the computer or to peripheral equipment.
High-speed main frame computers issue commands to transmit data to predetermined address locations of memory or logic cards at timed intervals less than 50 microseconds (u sec). If any of the many gates and latches malfunction during the designated transmission time, erroneous data may be placed on the bus. The wrong data may be transmitted at the right time or the wrong time and correct data may be transmitted at the wrong time. Such conditions would not be immediately detected by parity checking circuits which are designed to detect one bit errors in the data being transmitted.
Accordingly, it would be highly desirable to provide logical checking circuits which monitor cards or elements of a CPU or MSU to determine if the card designated to transmit data is the only card which is made capable of transmitting data during the time period allowed for the transmission of the data from the designated card.